International Journal of Engineering
Trends and Technology

Research Article | Open Access | Download PDF
Volume 74 | Issue 2 | Year 2026 | Article Id. IJETT-V74I2P110 | DOI : https://doi.org/10.14445/22315381/IJETT-V74I2P110

Design and Implementation of Fast Fourier Transform Using Pipelining

A. Lakshmi, P.Chandrasekhar Reddy

Received Revised Accepted Published
06 Aug 2025 07 Jan 2026 20 Jan 2026 14 Feb 2026

Citation :

A. Lakshmi, P.Chandrasekhar Reddy, "Design and Implementation of Fast Fourier Transform Using Pipelining," International Journal of Engineering Trends and Technology (IJETT), vol. 74, no. 2, pp. 151-171, 2026. Crossref, https://doi.org/10.14445/22315381/IJETT-V74I2P110

Abstract

Innovative approaches to stable, high-throughput, and area-efficient communications in wireless fading settings are being driven by the quick development of broadband wireless applications. One of the most computationally demanding and power-hungry modules in the communication industry is the Fast Fourier Transform (FFT). The FFT has several essential uses, such as image filtering, data compression, signal analysis, and sound filtering. It is difficult to balance design criteria, including speed, power, area, flexibility, and scalability, while designing FFT hardware. A radix-2, 4-point FFT processor architecture is designed and implemented using backend tools in the work, as the full custom designs offer high performance. A Pipelined Multiplier is used to increase the speed of the design. The FFT processor has been designed and implemented using 90nm technology in Virtuoso schematic editor and layouts using Assura tools. The need for a new generation of digital processors, identified as the Fast Fourier Transform (FFT), capable of handling new requirements in signal processing, has mobilized the world of high-performance digital signal processing.

Keywords

Butterfly architecture, FFT, Full custom design, Multiplier, Pipeline, Radix-4.

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