Citation :

A. Lakshmi, P. Chandrasekhar Reddy, "Pipelined Hardware-Efficient Scalable Complex Multiplier for High-Performance DSP Applications," International Journal of Engineering Trends and Technology (IJETT), vol. 74, no. 2, pp. 88-97, 2026. Crossref, https://doi.org/10.14445/22315381/IJETT-V74I2P106

Abstract

Complex numbers find significant use in Very Large-Scale Integration (VLSI) design, particularly in Digital Signal Processing (DSP) algorithms and hardware implementations. They are crucial for efficiently performing complex mathematical operations like the Fast Fourier Transform (FFT) and other signal processing techniques. In any system, multipliers take a longer time to process due to complexity, and therefore, efficient design of multipliers is crucial in the overall performance of the system. A 16x18 and a 64x64 Hardware-efficient complex multiplier are designed, which uses fewer multipliers than the direct approach. The design is suitable for high-speed applications because of its pipelined architecture, and its parameterized sizes of inputs offer scalability of designs with customized and target applications. This design also offers low power and minimum area to serve the very purpose of SoC, and even as an IP Core. The design is implemented in 90nm technology using the Cadence design suite. Thus, the design furnished reduces the number of operations at the architectural level itself and can save chip area, power, cost, and further increase speed.

Keywords

Complex multiplier, Hardware-efficient, Pipeline, SoC, VLSI.

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