Design and Implementation of High Throughput and Efficient FIR Filter Architectures using Unfolding

Design and Implementation of High Throughput and Efficient FIR Filter Architectures using Unfolding
  IJETT-book-cover           
  
© 2024 by IJETT Journal
Volume-72 Issue-8
Year of Publication : 2024
Author : Braj Kishor, Krishna Raj
DOI : 10.14445/22315381/IJETT-V72I8P139

How to Cite?
Braj Kishor, Krishna Raj, "Design and Implementation of High Throughput and Efficient FIR Filter Architectures using Unfolding," International Journal of Engineering Trends and Technology, vol. 72, no. 8, pp. 429-438, 2024. Crossref, https://doi.org/10.14445/22315381/IJETT-V72I8P139

Abstract
The unfolding technique can be used to generate word-level parallel processing architectures as it uses fewer clock cycles to compute an output sample. This paper aims to design and implement word-level parallel processing architectures for 2-tap, 4-tap and 11-tap serial low-pass FIR (Finite Impulse Response) filters. To improve the throughput of the proposed architectures, data broadcast types serial FIR filters were used. An unfolding factor with the value of two is taken for designing 2-unfolded architectures for the original serial FIR filter architectures. Proposed 2-unfolded architectures operate at 1200 KHz, and inputs for 2-unfolded architectures are generated by a serial-to-parallel converter circuit at a frequency of 2400KHz. FPGA (Field Programmable Gate Array) system clock is used to generate these frequencies. VHDL (Very High Speed Integrated Circuit HDL) language is used to design 2- unfolded architectures, and Xilinx Vivado 2015.2 tool is used to implement these architectures on the Artix7 Basys3 FPGA board. Designed and implemented 2-unfolded architectures are compared with existing serial and parallel FIR filter architectures.

Keywords
FIR filter, Unfolding, Parallel processing, FPGA, VHDL, Throughput.

References
[1] Keshab K. Parhi, VLSI Digital Signal Processing Systems Design and Implementation, Wiley, pp. 1-808, 2007.
[Google Scholar] [Publisher Link]
[2] Alfred V. Aho, Ravi Sethi, and Jeffrey D. Ullman, Compilers, Principles, Techniques, and Tools, Addison-Wesley Publishing Company, pp. 1-796, 1986.
[Google Scholar] [Publisher Link]
[3] K.K. Parhi, and D.G. Messerschmitt, “Pipeline Interleaving and Parallelism in Recursive Digital Filters. I. Pipelining Using Scattered Look-Ahead and Decomposition,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37, no.7, pp. 1099-1117, 1989.
[CrossRef] [Google Scholar] [Publisher Link]
[4] K.K. Parhi, and D.G. Messerschmitt, “Pipeline Interleaving and Parallelism in Recursive Digital Filters. II. Pipelined Incremental Block Filtering,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37, no. 7, pp. 1118-1135, 1989.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, “Low-Power CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, 1992.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Manoj Kumar, and Karni Ram, “Implementation of Word Level Parallel Processing Unfolding Algorithm Using VHDL,” International Journal of Engineering and Advanced Technology, vol. 8, no. 6, pp. 664-667, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[7] S.K. Manikandan et al., “High Throughput LFSR Design for BCH Encoder Using Sample Period Reduction Technique for MLC NAND Based Flash Memories,” International Journal of Computer Applications, vol. 66, no. 10, pp. 33-39, 2013.
[Google Scholar] [Publisher Link]
[8] Sangeeta Singh et al., “VLSI Implementation of Parallel CRC Using Pipelining, Unfolding and Retiming,” IOSR Journal of VLSI and Signal Processing, vol. 2, no. 5, pp. 66-72, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Daimond Soibam Singh, and Manoj Kumar, “Design and Implementation of Third Order Low Pass Digital FIR Filter Using Pipelining Retiming Technique,” International Journal of Engineering and Advanced Technology, vol. 10, no. 4, pp. 178-184, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Tamli Dhanraj Sawarkar, Lokesh Chawle, and N.G. Narole, “Implementation of 4-Tap Sequential and Parallel Micro-Programmed Based Digital FIR Filter Architecture Using VHDL,” International Journal of Innovative Research in Computer and Communication Engineering, vol. 4, no. 4, pp. 6906-6913, 2016.
[Google Scholar] [Publisher Link]
[11] R. Saranya, “FPGA Synthesis of Reconfigurable Modules for FIR Filter,” International Journal of Reconfigurable and Embedded Systems, vol. 4, no. 2, pp. 63-70, 2015.
[Google Scholar] [Publisher Link]
[12] L. Kholee Phimu, and Manoj Kumar, “VLSI Implementation of Area Efficient 2-Parallel FIR Digital Filter,” International Journal of VLSI design & Communication Systems, vol. 7, no. 5/6, pp. 17-24, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[13] N. Sankarayya, K. Roy, and D. Bhattacharya, “Algorithms for Low Power and High Speed FIR Filter Realization Using Differential Coefficients,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 6, pp. 488-497, 1997.
[CrossRef] [Google Scholar] [Publisher Link]