Prototype Design and Analysis of 4-Stage Operational-Amplifier using Double-Gate MOSFET

Prototype Design and Analysis of 4-Stage Operational-Amplifier using Double-Gate MOSFET
  IJETT-book-cover           
  
© 2023 by IJETT Journal
Volume-71 Issue-7
Year of Publication : 2023
Author : Joshua T. Ramdeo, Viranjay M. Srivastava
DOI : 10.14445/22315381/IJETT-V71I7P217

How to Cite?

Joshua T. Ramdeo, Viranjay M. Srivastava, "Prototype Design and Analysis of 4-Stage Operational-Amplifier using Double-Gate MOSFET," International Journal of Engineering Trends and Technology, vol. 71, no. 7, pp. 175-188, 2023. Crossref, https://doi.org/10.14445/22315381/IJETT-V71I7P217

Abstract
This research work designs a 4-stage operational amplifier (op-amp) using Double-Gate (DG) MOSFETs. The DG MOSFET has various advantages over the traditional single-gate MOSFET. These advantages can provide the op-amp with more stability. A feasible solution has been proposed based on the design and analysis. Thereafter, a prototype has been fabricated and realized. The prototype has been tested, and various parameters have been analyzed, such as the output voltage, CMRR, slew rate, voltage losses, etc. The achieved voltage loss is 0.08 V, slew rate of 0.0549 V/µs, which is suitable for nanoelectronics device applications.

Keywords
Double-gate MOSFET, Operational-amplifier, Differential amplifier, Low energy device, Microelectronics, Nanotechnology, VLSI.

References
[1] International Roadmap for Devices and Systems (IRDS), From Moore’s Law to NTRS to ITRS to IRDS, 2020. [Online]. Available: https://irds.ieee.org/
[2] Yannis Tsividis, and Colin McAndrew, Operation and Modeling of the MOS Transistor, Oxford University Press, 2010.
[Google Scholar] [Publisher Link]
[3] Jean-Pierre Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.
[Google Scholar] [Publisher Link]
[4] Naveenbalaji Gowthaman, and Viranjay M. Srivastava, “Mathematical Modeling of Electron Density Arrangement in CSDG MOSFET: A Nano-Material Approach,” Journal of Materials Science, vol. 57, no. 18, pp. 8381-8392, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Guoyong Shi, “Sizing of Multi-Stage Op-Amps by Combining Design Equations with the gm/ID Method,” Integration, vol. 79, pp. 48-60, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Amirhossein Rasekh, and M. Sharif Bakhtiar, “Compensation Method for Multi-Stage Opamps with High Capacitive Load Using Negative Capacitance,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 63, no. 10, pp. 919 – 923, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Anand Kumar et al., “Comparative Performance Study of Difference Differential Amplifier using 7 nm and 14 nm FinfET Technologies and Carbon Nanotube FET,” Functional Graded Nanomaterials, vol. 2022, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Behnam Babazadeh Daryan et al., “Multi-Stage CMOS Amplifier Frequency Compensation using a Single MOSCAP,” Analog Integrated Circuits and Signal Processing, vol. 103, pp. 237–246, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Po Yu Kuo, and Sheng Da Tsai, “An Enhanced Scheme of Multi-Stage Amplifier with High-Speed High-Gain Blocks and Recycling Frequency Cascode Circuitry to Improve Gain-Bandwidth and Slew Rate,” IEEE Access, vol. 7, pp. 130820-130829, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Guoyong Shi, “Symbolic Distortion Analysis of Multi-Stage Amplifiers,” IEEE Transactions on Circuits and Systems, vol. 66, no. 1, pp. 369-382, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Shubin Liu et al., “A 1.2-V 2.41-GHz Three-stage CMOS OTA with Efficient Frequency Compensation Technique,” IEEE Transactions on Circuits and Systems, vol. 66, no. 1, pp. 20-30, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Jian Long Wang et al., “Analysis and Design of Operational Amplifier Stability Based on Routh-Hurwitz Method,” 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-3, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Sadegh Biabanifard et al., “Multi-Stage OTA Design: From Matrix Description to Circuit Realization,” Microelectronics Journal, vol. 77, pp. 49-65, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Kandi P. Kumar, and D Vaithiyanathan, “Design and Analysis of a Three Stage CMOS op-amp using Indirect Feedback Compensation,” Journal of Physics, vol. 1706, pp. 1-7, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[15] Sadegh Biabanifard et al., “Three Stages CMOS Operational Amplifier Frequency Compensation using Single Miller Capacitor and Differential Feedback Path,” Analog Integrated Circuits and Signal Processing, vol. 97, pp. 195–205, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[16] Elliot O. Omoru, and Viranjay M. Srivastava, “Testing and Analysis of MOSFET Based Absorber Integrated Antenna for 5G/WiMAX/WLAN Applications,” Nanomaterials, vol. 12, no. 17, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Adel S. Sedra, and Kenneth C. Smith, Microelectronics Circuits: Theory and Applications, 7th Edition, Oxford University Press, 2014.
[Google Scholar]
[18] S.A. Pactitis, Active filters: Theory and Design, CRC Press, 2011.
[Google Scholar]
[19] Dattaguru V. Kamat, “New Operational Amplifier Based Inverse Filters,” 3rd International Conference on Electronics, Communication and Aerospace Technology, pp. 1177-1181, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[20] M. R. Jyoti, H. Chetan, and Manjudevi, “Design and Performance Analysis of Differential Amplifier for Various Applications,” Journal of Computational and Theoretical Nanoscience, vol. 15, no. 11-12, pp. 3501-3508, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Po Y. Kuo, and Sheng Da Tsai, “An Enhanced Scheme of Multi-Stage Amplifier with High-Speed High-Gain Blocks and Recycling Frequency Cascode Circuitry to Improve Gain-Bandwidth and Slew Rate,” IEEE Access, vol. 7, pp. 130820 – 130829, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[22] Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Double-Pole Four-Throw RF CMOS Switch Design with Double-Gate Transistors,” Annual IEEE India Council Conference, pp. 1-4, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[23] Keita Tachiki et al., “Short-Channel Effects in SIC MOSFETs based on Analyses of Saturation Drain current,” IEEE Transactions on Electron Devices, vol. 68, no. 3, pp. 1382-1384, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[24] Nikolaos Makris et al., “Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction Fets—Part I: Drain Current and Transconductances,” IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2744-2750, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[25] Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Double Pole Four Throw Switch Design with CMOS Inverter,” 5th IEEE International Conference on Wireless Communication and Sensor Networks, pp. 1-4, 2009.
[CrossRef] [Google Scholar] [Publisher Link]
[26] P. M. Solomon et al., “Two Gates are Better Than One [double-gate MOSFET process],” IEEE Circuits and Devices Magazine, vol. 19, no. 1, pp. 48 – 62, 2003.
[CrossRef] [Google Scholar] [Publisher Link]
[27] Yuan Taur and Huang-Hsuan Lin, “Modeling of DG MOSFET I–V Characteristics in the Saturation Region,” IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 1714-1720, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[28] S.Archana, G.Vallathan and M.Anantha Kumar, “Analytical Modeling of Dual Material Junctionless Surrounding Gate MOSFET,” SSRG International Journal of Electronics and Communication Engineering, vol. 4, no. 3, pp. 22-25, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[29] Discrete Semiconductors, BF998; BF998R Silicon N-Channel Dual Gate MOSFET Datasheet, NXP Semiconductors, 1996. [Online]. Available: https://www.nxp.com/docs/en/data-sheet/BF998.pdf
[30] Product Data Sheet, BF909; BF909R N-Channel Dual Gate MOS-FETs Datasheet, NXP Semiconductors, 2007. [Online]. Available: https://www.nxp.com/docs/en/data-sheet/BF909_N.pdf
[31] Viranjay M. Srivastava and Ghanshyam Singh, MOSFET Technologies for Double-Pole Four Throw Radio Frequency Switch, Springer International Publishing, 2014. [CrossRef] [Google Scholar] [Publisher Link]
[32] Igor B. Shirokov, “Increasing of Operation Range of System of RFID and Positioning,” IEEE Journal of Radio Frequency Identification, vol. 4, no. 4, pp. 444-451, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[33] Uttam Kumar Das, and Tarun Kanti Bhattacharyya, “Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET versus GAA-FET versus UFET,” IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2633-2638, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[34] Ahmed Abdelmoneam, Benjamin Iniguez, and Mostafa Fedawy, “Compact Modelling of Quantum Confinement in III-V Gate all Around Nanowire MOSFET,” Spanish Conference on Electron Devices (CDE), pp. 1-4, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[35] Viranjay M. Srivastava, “Relevance of VEE Programming for Measurement of MOS Device Parameters,” IEEE International Advance Computing Conference, pp. 205-209, 2009.
[Google Scholar]
[36] Igor B. Shirokov, “Increasing of Operation Range of RFID System,” IEEE International Conference on RFID Technology and Applications, pp. 337-341, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[37] Suvashan Pillay, and Viranjay M. Srivastava, “Design and Comparative Analysis of Active-Loaded Differential Amplifier Using Double-Gate MOSFET,” SN Applied Science, vol. 4, no. 8, pp. 1-15, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[38] Juan M. Carrillo et al., “Low-Power Wide-Bandwidth CMOS Indirect Current Feedback Instrumentation Amplifier,” AEU-International Journal of Electronics and Communications, vol. 123, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[39] Amol S. Sankpal, and D.J. Pete, “Optimization of Retention Time in 3T DRAM using Anti-Body Bias Technique in Nanoscale Technology,” International Journal of Engineering Trends and Technology, vol. 70, no. 11, pp. 378-392, 2022.
[CrossRef] [Publisher Link]
[40] Selvakumar Rajendran et al., “A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques,” Recent Advances in Electrical & Electronic Engineering, vol. 14, no. 4, pp. 377-397, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[41] Bhawna Aggarwal, Maneesha Gupta, and A. K. Gupta, “A Comparative Study of Various Current Mirror Configurations: Topologies and Characteristics,” Microelectronics Journal, vol. 53, pp. 134-155, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[42]S. Saranya et al., “A Review on Analysis of Performance Parameters in Low Voltage Current Mirror Circuits,” Advances in Materials Research, vol. 5, pp. 1069–1077, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[43] Ramakant A. Gayakwad, Op-Amps and Linear Integrated Circuits, 4th Edition, Pearson, 2015.
[Google Scholar]
[44] Leila Safari et al., “Traditional Op-Amp and new VCII: A Comparison on Analog Circuits Applications,” AEU-International Journal of Electronics and Communications, vol. 110, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[45] Ling Lu, “Topology on a Breadboard,” Nature Physics, vol. 14, pp. 875–877, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[46] Paul R. Gray et al., “Analysis and Design of Analog Integrated Circuits, 5th Edition, Wiley, 2009.
[Google Scholar]
[47] Eric Macdonald et al., “3D Printing for the Rapid Prototyping of Structural Electronics,” IEEE Access, vol. 2, pp. 234-242, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[48] R. S. Khandpur, Printed Circuit Boards: Design, Fabrication, Assembly and Testing, Tata McGraw-Hill Education, 2005.
[Google Scholar]
[49] Naveenbalaji Gowthaman, and Viranjay M. Srivastava, “Mathematical Modeling of Drain Current Estimation in a CSDG MOSFET, Based on La2o3 Oxide Layer with Fabrication—A Nanomaterial Approach,” Nanomaterials, vol. 12, no. 19, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[50] R. Jaeger, and T. Blalock, Current Mirrors, Microelectronic Circuit Design, 4th Edition, pp. 1042-1079, 2011.