Citation :

Pradnya Zode, Pravin Zode, Nilesh Ashtankar, Nilesh Shelke, "Advanced Design Approaches for Bit- and Digit-Level Systolic Array Multiplication," International Journal of Engineering Trends and Technology (IJETT), vol. 74, no. 5, pp. 205-218, 2026. Crossref, https://doi.org/10.14445/22315381/IJETT-V74I5P114

Abstract

This paper emphasizes advanced Architectural Designs of multipliers using systolic arrays explicitly augmented for Bit and Digit-Level Multiplication. These array multipliers are appropriate for high-speed, low area as well as parallel multiplication applications like Digital Signal Processing, Cryptography, and Artificial Intelligence. The array multipliers have a regular structure with efficient and very small interconnections so that the incoming real-time data can flow in a pipelined manner. With respect to this, different types of array multiplier with bit serial and digit serial processing methods are designed. The designed structures are assigned different mixtures of binary numbers as an input for finding the proper product bits. Advanced Bit-Level and Digit-Level with size two are developed and synthesized for 8 by 8 bits carry save array, Carry Ripple Array, and Baugh-Woolley multiplier. Towards this, dependence graphs for all the arrays of all multipliers are also designed in Verilog and synthesized on the board Xilinx ML605 (Virtex 6 XC6VLX240T-1FFG1156 FPGA). The detailed performance comparison between regular Carry Save, Carry Ripple, and Baugh-Wooley array multipliers examines the competence of these three different multiplier architectures using significant recital metrics such as delay, power consumption, and area utilization with the different word lengths from 4-bit to 128-bit. Out of these three, Baugh-Wooley array multipliers steadily deliver the maximum improvement in delay, with up to 55.02% at 4-bit and 38.51% at 128-bit. It also displays impactful enhancements in power up to 43.72% and area up to 35.24% than both carry save and Carry Ripple Array multiplier. Carry Ripple Array multiplier demonstrations reasonable enhancements, predominantly in power (up to 37.4% at 4-bit), but less significant than Baugh-Wooly. As word length intensifications, Baugh-Wooley’s array multiplier proficiency governs across all three systems of measurement. These results highlight Baugh-Wooley’s appropriateness for high-speed, low-power, and area-efficient VLSI designs.

Keywords

Systolic arrays, bit and digit level, Array multiplier, Carry save array, Carry ripple array, Baugh-Wooley multiplier dependence graph.

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