Analysis and Optimal Design of Power-Efficient and High-Stable Proposed SRAM Cell
Analysis and Optimal Design of Power-Efficient and High-Stable Proposed SRAM Cell |
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| © 2023 by IJETT Journal | ||
| Volume-71 Issue-6 |
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| Year of Publication : 2023 | ||
| Author : Deepika Sharma, Shilpi Birla |
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| DOI : 10.14445/22315381/IJETT-V71I6P229 | ||
How to Cite?
Deepika Sharma, Shilpi Birla , "Analysis and Optimal Design of Power-Efficient and High-Stable Proposed SRAM Cell," International Journal of Engineering Trends and Technology, vol. 71, no. 6, pp. 289-302, 2023. Crossref, https://doi.org/10.14445/22315381/IJETT-V71I6P229
Abstract
Power dissipation is the key challenge of today’s IC design, which reduces the lifetime of battery-operated devices. Continuous scaling of CMOS technology reduces the channel length and increases the static power dissipation. Leakage is the dominating factor in memory design which contributes almost 40-50% of overall power dissipation. In today’s high-performance design, leakage power is almost equal to dynamic or switching power. Almost 40% or more of total power consumption is due to the leakage power of the transistor, and this factor is increasing day by day with the scaling of technology until some effective methods are introduced for leakage controls. Memory designs require a good noise margin for the stability of SRAM cells. Higher the value of noise margins higher the speed of SRAM cells. The main aims of this study are to simulate various topologies of 10T and 6T SRAM cell design using CMOS and FinFET technology and evaluate their performance for comparisons. Different techniques are applied for power reduction at lower operating voltage. Evaluated results are also compared with 6T SRAM cells for a better understanding of the results. There is 37%, 73% and 19% improvement in HSNM, RSNM, and WSNM, respectively, in 10T SRAM cells compared to conventional 6T cells. HSPICE tool at 32nm technology is used for simulation.
Keywords
CMOS, FinFET, HSNM, MTCMOS, SCE.
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