Design and Implementation of C/A code Generation for SOC-based GNSS-SDR Applications

Design and Implementation of C/A code Generation for SOC-based GNSS-SDR Applications
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© 2023 by IJETT Journal
Volume-71 Issue-4
Year of Publication : 2023
Author : Arunalatha Botla, G Kanaka Durga, Chandrasekhar paidimarry
DOI : 10.14445/22315381/IJETT-V71I4P212

How to Cite?

Arunalatha Botla, G Kanaka Durga, Chandrasekhar paidimarry, " Design and Implementation of C/A code Generation for SOC-based GNSS-SDR Applications ," International Journal of Engineering Trends and Technology, vol. 71, no. 4, pp. 128-139, 2023. Crossref, https://doi.org/10.14445/22315381/IJETT-V71I4P212

Abstract
GNSS receivers may now be found in a variety of miniaturised platforms, chipsets, microprocessors, Integrated Chips (IC), DSPs, FPGAs, portable devices, and even the majority of mobile phones. This trend is expected to continue in the near future. In point of fact, GNSS receivers may run on a diverse range of platforms. This flexibility is achieved by a careful balancing act between a number of factors, including receiver performance, cost, power consumption, and battery life. In addition, the growing capabilities of microprocessors have made it possible for software receivers to emerge with performance comparable to that of implemented hardware receivers. This has provided certain user applications with the flexibility that is required for them to function properly. This work aims to demonstrate the GNSS software receiver architecture, which can receive all of the GNSS signals currently being received by the antenna at any given time. This article presents a discussion on the most recent developments in GNSS receiver designs. The primary block of GPS and GLONASS has been implemented in both Matlab as well as Xilinx Vivado tools.

Keywords
GNSS-SDR, SDR architectures, GPS, GLONASS, SoC.

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